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| SA58646 UHF 900 MHz transceiver IC Rev. 01 -- 8 February 2007 Product data sheet 1. General description The SA58646 is a BiCMOS integrated circuit that performs all functions from the antenna to the microcontroller for reception and transmission for both the base station and the handset in a 902 MHz to 928 MHz full-duplex radio. The SA58646 may be used in a UHF push-to-talk walkie-talkie or in a UHF to 900 MHz data transceiver. The SA58646 is a pin-compatible derivative of the UAA3515 with advanced features. This IC integrates most of the functions required for a half-duplex or full-duplex radio in a single integrated circuit. Additionally, the programmability implemented reduces significantly external components count, board space requirements and external adjustments. 2. Features I RF RX (single frequency conversion FM receiver): N Integrated LNA N Image reject mixer N FM detector at 10.7 MHz including an IF limiter, a wide band PLL demodulator, an output amplifier and a RSSI output N Carrier detection with programmable threshold N Programmable data amplifier (slicer) phase I Synthesizer: N Crystal reference oscillator with integrated tuning capacitor N Reference frequency divider N Narrow band RX PLL including RX VCO with integrated varicaps N Narrow band TX PLL including TX VCO with integrated varicaps N VCO external inductors can be done with printed transmission lines on the PCB which offers substantial savings N Programmable clock divider with output buffer to drive a microcontroller I Baseband RX section: N Programmable RX gain (enable phone volume control) N Expander with output noise level control N Earpiece amplifier with volume control feature N Data amplifier I Baseband TX section: N Microphone amplifier N Compressor with automatic level control and hard limiter N Programmable TX gain NXP Semiconductors SA58646 UHF 900 MHz transceiver IC I Microcontroller interface: N 3-wire serial interface I Other features: N Voltage regulator to supply internal PLLs N Selectable voltage doubler N Programmable low battery detection time multiplexed with RSSI carrier detection 3. Applications I 902 MHz to 928 MHz full-duplex radio I UHF to 900 MHz data transceiver I UHF push-to-talk walkie-talkie 4. Ordering information Table 1. Ordering information Package Name SA58646BD LQFP64 Description plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Version SOT314-2 Type number SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 2 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 5. Block diagram IF 10.7 MHz IF 10.7 MHz IF 10.7 MHz GND(LNA) GND(MIX) 64 LNA 4 62 mixer 1 63 56 55 53 52 50 51 54 47 61 49 PLLO RFIX RFIY 2 3 VCC(BLO) amplifier VCC(LNA) VCC(MIX) GND(IF) VCC(IF) IFA1O IFA2O +90 IFamp1 IFamp2 limiter LPFD MIXO IFA1I IFA2I LIMI IF mixer PLL DEMODULATOR tune 48 DETO BAND PASS RSSI RSSI 7 RSSI DATA COMPARATOR QUADRATURE PHASE SHIFTER data amplifier 40 DATAI 39 DATAO MIXER RX-RF GNDVRX 60 VRX 57 RXLOY 59 RXLF 5 RXLOX 58 VCO RX VREG RX RX gain EXPANDER MUTE 44 VCC(ARX) 46 RXAI 45 ECAP SA58646 earpiece amplifier VB volume control 43 EARI 42 EARO RX-BB 41 GND(ARX) RXPD 6 XTALI 32 VCP RX PHASE DETECTOR 10-BIT 6-BIT MAIN RX PRESCALER DIVIDER RX 12 VCC(PS) XTALO 33 OSCILLATOR CLKO 35 CLOCK DIVIDER VCP VCP 10 GNDVCP 11 VOLTAGE DOUBLER 10-BIT REFERENCE DIVIDER VCP TX PHASE DETECTOR 10-BIT 6-BIT MAIN TX PRESCALER DIVIDER TX 13 TXPD SYNTHESIZER VCC(ATX) 24 GND(ATX) 31 MICI 27 MICO 28 VB microphone amplifier TX-BB TX-RF VCO TX 22 TXLOX 14 TXLF 23 TXLOY ALC 20 GNDVTX VB TX gain CMPI 29 CCAP 25 PA 15, 17 GND(PA) COMPRESSOR HARD LIMITER MUTE summator VREG TX 21 VTX 16 PAO VB VREG VREG 8 VB 30 VOLTAGE REGULATOR CDLBD/ TEST LOW BATTERY DETECTOR 34 CDLBD LBD EN 36 DATA 38 CLK 37 MICROCONTROLLER SERIAL INTERFACE 9 GNDIG 26 TXO 18 MODI 19 MODO CD VCC VB RSSI VB OL RX/TX 001aaf616 Fig 1. Block diagram of SA58646 SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 3 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 6. Pinning information 6.1 Pinning 60 GNDVRX 61 VCC(BLO) 64 VCC(LNA) 62 VCC(MIX) 51 GND(IF) 59 RXLOY 58 RXLOX 54 VCC(IF) 53 IFA2I 52 IFA2O 55 IFA1O GND(MIX) RFIX RFIY GND(LNA) RXLF RXPD RSSI VREG GNDDIG 1 2 3 4 5 6 7 8 9 49 PLLO 63 MIXO 56 IFA1I 57 VRX 50 LIMI 48 DETO 47 LPFD 46 RXAI 45 ECAP 44 VCC(ARX) 43 EARI 42 EARO 41 GND(ARX) 40 DATAI 39 DATAO 38 DATA 37 CLK 36 EN 35 CLKO 34 CDLBD 33 XTALO SA58646BD VCP 10 GNDVCP 11 VCCPS 12 TXPD 13 TXLF 14 GND(PA) 15 PAO 16 GND(PA) 17 MODI 18 MODO 19 GNDVTX 20 VTX 21 TXLOX 22 TXLOY 23 VCC(ATX) 24 CCAP 25 TXO 26 MICI 27 MICO 28 CMPI 29 VB 30 GND(ATX) 31 XTALI 32 001aaf617 Fig 2. Pin configuration 6.2 Pin description Table 2. Symbol GND(MIX) RFIX RFIY GND(LNA) RXLF RXPD RSSI VREG GNDDIG VCP GNDVCP SA58646_1 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 Description mixer ground LNA input x LNA input y LNA ground RX loop filter output RX phase detector output RSSI output internal voltage regulator capacitor connection digital parts ground charge pump voltage output charge pump ground (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 4 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Pin description ...continued Pin 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Description prescaler supply TX phase detector output TX loop filter output PA ground PA output PA ground summator amplifier input summator amplifier output VCO TX ground VCO TX voltage output VCO TX coil connection x VCO TX coil connection y audio TX supply external capacitor connection for compressor audio TX output microphone amplifier input microphone amplifier output compressor input voltage reference capacitor connection audio TX ground crystal input crystal output carrier detector or low battery detector output (out-of-lock synthesizer RX and/or TX in Test mode) clock output serial interface enable input serial interface clock input serial interface data input data amplifier output data amplifier input audio RX ground earpiece amplifier output earpiece amplifier input audio RX supply external capacitor connection for expander audio RX input demodulator loop filter inverting demodulator amplifier output demodulator amplifier negative input limiter input IF ground (c) NXP B.V. 2007. All rights reserved. Table 2. Symbol VCC(PS) TXPD TXLF GND(PA) PAO GND(PA) MODI MODO GNDVTX VTX TXLOX TXLOY VCC(ATX) CCAP TXO MICI MICO CMPI VB GND(ATX) XTALI XTALO CDLBD CLKO EN CLK DATA DATAO DATAI GND(ARX) EARO EARI VCC(ARX) ECAP RXAI LPFD DETO PLLO LIMI GND(IF) SA58646_1 Product data sheet Rev. 01 -- 8 February 2007 5 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Pin description ...continued Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 Description IF second amplifier output IF second amplifier input IF supply IF first amplifier output IF first amplifier input VCO RX voltage output VCO RX coil connection x VCO RX coil connection y VCO RX ground RX LO buffer supply mixer supply mixer output LNA supply Table 2. Symbol IFA2O IFA2I VCC(IF) IFA1O IFA1I VRX RXLOX RXLOY GNDVRX VCC(BLO) VCC(MIX) MIXO VCC(LNA) SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 6 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 7. Functional description Refer to Figure 1 "Block diagram of SA58646". 7.1 Power supply and power management 7.1.1 Power supply voltage This circuit is used in a full-duplex radio handset and base unit. The handset unit is battery powered and can operate on three NiCad cells. The minimum supply voltage of the IC is VCC = 2.9 V. 7.1.2 Power-saving operation modes When the circuit is used in a handset, it is important to reduce the current consumption. There are 3 main modes of operation: * Active mode (talk): all blocks are powered * RX mode: all circuitry in the RF receiver part is active * Inactive mode: all circuitry is powered down except the serial interface. In this latter mode the crystal reference oscillator, output clock buffer, voltage regulator and voltage doubler can be disabled separately. A low current consumption mode on the crystal oscillator and clock output can be programmed. Latch memory is maintained in all modes. Table 3 shows which blocks are powered in each mode. Table 3. Powered blocks Mode Active VB reference RX-RF RX PLL RX and TX audio TX-RF (and PA if enabled) X X X X X RX X X X Inactive - Circuit block Some blocks can be activated separately: crystal oscillator, voltage regulator (adjustment is always disabled), power amplifier, voltage doubler, hard limiter, automatic level control, output clock buffer and earpiece amplifier. Table 4 shows which block can be activated in each mode. SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 7 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Activated blocks Mode Active RX X X X X X Inactive X X X X -[4] X X X X X X X active[2] Table 4. Circuit block Crystal active[1] Clock output not disabled Voltage regulator Doubler Power amplifier active enabled[3] Hard limiter or automatic level control not disabled Earpiece amplifier enabled [1] [2] [3] [4] In RX and TX mode, the crystal oscillator is automatically activated. An external frequency can be forced to pins XTALI and XTALO. In RX and TX mode, the voltage regulator with adjustment is automatically enabled; bit REG can be either logic 1 or logic 0. If the voltage doubler is enabled, the crystal oscillator is automatically activated. In Inactive mode, the earpiece amplifier is automatically disabled. 7.1.3 Control bits in power saving modes Table 5 shows the control bit values for selection of each mode and the typical current consumption for those modes. Table 5. Control bit values VCC = 3.3 V; Tamb = 25 C; fxtal = 10.24 MHz. Power saving MODE[1:0] mode Bit 1 Bit 0 Active mode RX mode Inactive mode 1 1 0 1 0 X Conditions Voltage doubler inactive Crystal oscillator disabled XTAL_H = 0 XTAL_H = 1 inactive active XTAL_H = 1 enabled disabled Voltage regulator disabled Clock output disabled Typical current consumption 76 mA 58 mA < 10 A 210 A 300 A 550 A 690 A When the clock output is activated, an extra power consumption is applied which is proportional to the programmed bit CLKO. If bit XTAL_H = 0, then the crystal loss is less than 50 to ensure reliable start-up. Table 6. Extra power consumption Extra current consumption Bit CLKO = 0 520 A 0 A Bit CLKO = 1 350 A 0 A Divider ratio Bits CLK_DIV[2:0] XXX (1, 2, 2.5, 4, 128) 000 (off) SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 8 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 7.2 FM receiver part The FM receiver has a single frequency conversion architecture. The image reject mixer enables the user to save an RF filter. The side band select feature (bit SBS) enables the user to choose its frequency plan with RX LO in or out of ISM band and have the same IC for both base and handset. An IF channel filtering compromise between price and performance can be achieved using two or three 10.7 MHz external filters. The integrated FM PLL demodulator with limiter enables consistent saving on external components and pins. The data comparator is an inverting hysteresis comparator. The open-collector output is current limited to control the output signal slew rate. An external band-pass filter is connected between pins DETO and DATAI (AC coupled). The external resistor should be 180 k at maximum VCC. An external capacitor can be added to further reduce the slew rate. IF 10.7 MHz IF 10.7 MHz IF 10.7 MHz MIXO IFA1I IFA1O IFA2I IFA2O LIMI DEM_FIL LPFD SFS mixer +90 LNA RFIX RFIY IFamp1 mixer VCO IFamp2 limiter mixer LOOP FILTER SBS QUADRATURE PHASE SHIFTER RXLOX RXLOY D_PHASE FM_PLL_VCO [4:0] amplifier DETO PLLO DUAL PLL FREQUENCY SYNTHESIZER CAR_DET_LEV [4:0] XTAL VREG RX VCO RX BAT_DET DATAO RXPD RXLOX LPF RXLF RXLOY VRX RSSI CDLBD RSSI VB data amplifier DATAI 001aaf618 Fig 3. FM receiver part SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 9 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 7.3 Transmitter part The transmitter architecture is of the direct modulation type. The transmit VCO will be frequency modulated by either speech or data (see Figure 4). Before the VCO, an amplifier sums the modulating signal and the data TX signal. VCO varicaps are integrated. External inductors that are in series with bonding wires and lead frame are needed to obtain the right frequency. The power amplifier is capable of driving 50 . The output level is programmed through the serial bus interface. MODI data TX TXO VB XTAL DUAL PLL FREQUENCY SYNTHESIZER summator amplifier MODO PA VCO TX PA_OUT [2:0] PAO VREG TX TXPD TXLOX TXLF TXLOY VTX 001aaf619 Fig 4. Transmit part 7.4 Synthesizer The crystal local oscillator and reference divider provide the reference frequency for the RX and TX PLLs. The 10-bit programmed divider value for the reference divider is selected based on the crystal frequency, the desired RX and TX reference frequency values. The crystal frequency of 16.348 MHz is chosen to provide to the microcontroller the standard 4.096 MHz frequency when programming the clock divider value to 4. Then the 16.384 MHz crystal frequency is proposed. The clock divider value will be programmed to 1, 2, 2.5, 4 and 128. The clock divider value of 128 is chosen to place the SA58646 in Sleep mode which enables current saving in the microcontroller. The clock output is an emitter follower type. The 16-bit TX counter is programmed for the desired transmit channel frequency. The 16-bit RX counter is programmed for the desired local oscillator frequency. The counters are built with a 6-bit prescaler (divider value R from 64 to 127) and a 10-bit divider (divider value C from 8 to 1023). The full counter then provides a divider value from 512 to 65535. To calculate the settings of the two counters, the following procedure is used: C = int (M / 64) R = M - C x 64 where M being the division ratio between the VCO frequency and the reference frequency. SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 10 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Example: RF RX f = 903 MHz, VCO RX f = 892.3 MHz, IF f = 10.7 MHz, VCO TX f = 925.6 MHz and the internal comparison frequency f = 20 kHz (fxtal = 10.24 MHz): REF_DIV[9:0] = 512 (10 0000 0000), For RX: M = 892.3 x 106 / 20 x 103 = 44615, C = 697 (10 1011 1001), R = 7 (00 0111), For TX: M = 925.6 x 106 / 20 x 103 = 46280, C = 723 (10 1101 0011), R = 8 (00 1000). VCOs and varicaps are integrated. The total equivalent inductance is comprised of the bonding wires, lead frame of the package and external inductors. External inductors can be done with printed transmission lines on the PCB, which allows substantial savings. An on-chip selectable voltage doubler is provided to enable a larger tuning range of the VCOs. The phase detectors have current drive type outputs. Current can be chosen between 400 A and 800 A. RX_CP XTAL_H RX PHASE DETECTOR XTAL RXLOX mixer VCO RX CLK_DIV [2:0] CLOCK DIVIDER CLKO VCP GNDVCP VOLTAGE DOUBLER REF_DIV [9:0] DOUBLER TX_CP TXLOX VOLTAGE REGULATOR REG REG_ADJ [2:0] TX_MDIV [9:0] 10-BIT MAIN TX DIVIDER TX_PRE [5:0] 6-BIT PRESCALER TX VCO TX TXLF TXLOY TX PHASE DETECTOR TXPD 10-BIT REFERENCE DIVIDER RX_MDIV [9:0] RX_PRE [5:0] RXLF RXLOY RXPD XTALO XTALI XTAL_TUN [3:0] CLKO 10-BIT 6-BIT MAIN RX PRESCALER DIVIDER RX VREG RX VRX VREG VB VREG TX VTX 001aaf620 PA MODO Fig 5. Synthesizer part SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 11 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 7.5 RX baseband This section covers the RX audio path from pins RXAI to EARO. The RXAI input signal is AC-coupled. The microcontroller sets the value of the RX gain with 32 linear steps of 0.5 dB. The RX baseband has a mute and an expander with the characteristics shown in Figure 7. The audio level is programmable over a dynamic range of 31 dB by the RX gain control. The expander slope multiplies the RX gain step by 2 to achieve 1 dB steps on the earpiece output. Noise coming from, and within, the RX baseband can be shaped thanks to a `noise control' programmability. It provides the possibility to attenuate the expander gain at low input level. Figure 7 provides some information about the noise shaper function. The earpiece amplifier is an inverting rail-to-rail operational amplifier. The non-inverting input is connected to the internal VB reference voltage. Software volume control on the earpiece amplifier is done by integrated switched feedback resistances. Volume control tuning range is 14 dB. Hardware volume control is done by externally switching the earpiece feedback resistance. EARI EARP_VOL [1:0] RX gain RXAI RX_GAIN [4:0] MUTE EXPANDER VB RX_MU EXP[1:0] ECAP EARP 001aaf621 earpiece amplifier EARO Fig 6. RX baseband part VEARO (dBV) 0 -10 -20 -30 -40 -50 -60 -45 -40 -30 -20 EXPDRout = -7 dBV (typical at THD < 4 %) y = 2x + 20 noise shaping -10 0 10 VRXAI (dBV) 001aaf622 RX gain adjustment at 0 dB; volume earpiece at 0 dB; no external resistance. Fig 7. Expander characteristic SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 12 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 7.6 TX baseband This section covers the TX audio path from pins MICI to TXO. The input signal at pin MICI is AC-coupled. The microphone amplifier output is also AC-coupled. The microphone amplifier is an inverting operational amplifier whose gain can be set by external resistors. The non-inverting input is connected to the internal VB reference voltage. External resistors are used to set the gain and frequency response. The TX baseband has a compressor with the characteristic shown in Figure 9. The Automatic Level Control (ALC) provides a `soft' limit to the output signal swing as the input voltage increases slowly (that is, a sine wave is maintained at the output). A hard limiter clamps the compressor output voltage at 1.26 V (p-p). The ALC and hard limiter can be disabled via the microcontroller interface. The hard limiter is followed by a mute. The TX gain is digitally programmable with 32 steps of 0.5 dB. MICO CMPI ALC ALC TX gain COMPRESSOR HARD LIMITER HD_LIM CCAP 001aaf623 MICI VB microphone amplifier MUTE TX_GAIN [4:0] TXO TX_MU Fig 8. TX baseband part VTXO (dBV) 0 -10 y = 0.5x - 5 -20 -30 -40 hard limiting signals: VCMPI = -4 dBV VTXO = 1.26 V (p-p) VCMPI = -2.5 dBV VTXO = -11.5 dBV slowly changing ALC signals: VCMPI = -16 dBV VTXO = -13 dBV -60 -50 -40 -30 -20 -10 0 VCMPI (dBV) 001aaf624 Fig 9. Compressor characteristic SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 13 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 7.7 Other features 7.7.1 Voltage regulator Regulator voltage VREG is the internal supply for the RX and TX PLLs. It is regulated at 2.7 V nominal voltage. Two capacitors with 4.7 F and 100 nF values must be connected to pin VREG to filter and stabilize this regulated voltage. The tolerance of the regulated voltage is initially 8 % but is improved to 2 % after the internal band gap voltage reference is adjusted via the microcontroller interface. In Inactive mode, the regulator voltage adjustment is automatically disabled. 7.7.2 Low battery detector The low battery detector measures the supply voltage VCC with a resistor divider and a comparator. One input of the comparator is connected to reference voltage VB and the other is connected to the middle point of the resistor divider. To prevent spurious switching the comparator has a built-in hysteresis. The precision of the detection depends on the divider accuracy, the comparator offset and the accuracy of the reference voltage. The output is multiplexed at pin CDLBD. When the battery voltage level is under the threshold voltage, the CDLBD output is set at LOW level. 7.8 Microcontroller serial interface The serial interface is used for programming the IC. To program the IC, 19 bits are used: 16 bits for data and 3 bits for register addresses. The serial interface requires 3 pins: DATA, CLK, EN (see Figure 10). The serial interface pins are supplied by regulator voltage VREG. The ESD protection diodes on these pins are connected to the supply voltage VCC. Digital outputs (CDLBD and DATAO) have open-collector or open-drain; CLKO is an emitter-follower output. The DATA, CLK and EN pins provide a 3-wire unidirectional serial interface for programming the reference counters, the transmit and receive channel divider counters, and the control functions. The interface consists of 19-bit shift registers connected to a matrix of registers organized as 7 words of 16 bits (all control registers). The data is entered with the most significant bit first. The leading 16 bits include the data (D15 to D0), while the trailing 3 bits set up the address (AD2 to AD0). The first bit entered is D15, the last bit AD0. The DATA and CLK pins are used to load data into the shift registers. Data is clocked into the shift registers on negative clock transitions. A new clock divider ratio is enabled thanks to an extra EN rising edge. Minimum hold time is 50 ns. During that time, no clock cycle is allowed. These extra EN edges can be applied to all the data programmed, but will have no effect on the serial interface programming. 8. Data registers and addresses D15 is the most significant bit, and is written first. Table 7 shows the data latches and addresses which are used to select each of the registers. SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 14 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 01 -- 8 February 2007 (c) NXP B.V. 2007. All rights reserved. SA58646_1 NXP Semiconductors Table 7. Addr 000 001 010 011 100 101 110 Data registers including preset values at power-on D15 SBS 0 D14 11 D13 D12 EARP 0 RX_PRE[5:0] XX XXXX [1] D11 D10 D9 0 1111 D8 D7 D6 SFS 1 D5 D_PHASE 0 D4 D3 D2 0 1111 D1 D0 EARP_VOL[1:0] RX_GAIN[4:0] FM_PLL_VCO[4:0] RX_MDIV[9:0] XX XXXX XXXX REF_DIV[9:0] XX XXXX XXXX TX_MDIV[9:0] XX XXXX XXXX TX_GAIN[4:0] 01111 CAR_DET_LEV[4:0] 0 0000 RX_CP 0 REG_ADJ[2:0] 011 EXP[1:0] 00 TX_MU 1 HD_LIM 0 L_BAT_DET[2:0] 000 TM0 0 [1] 00 0000 TX_PRE[5:0] XX XXXX TM2 0 REG 1 010 [1] CLKO 0 00 PA_OUT[2:0] TM1 0 DOUBLER 0 XTAL_H 1 TX_CP 0 ALC 0 XTAL 1 BAT_DET 1 RX_MU DEM_FIL 1 0 CLK_DIV[2:0] 100 XTAL_TUN[3:0] 0111 [1] 0 MODE[1:0] 0 Undefined zone should always be programmed with logic 0. UHF 900 MHz transceiver IC SA58646 15 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 8.1 Data register 0 Table 8. Data register 0 (address 000h) bit description Legend: * reset value. Bit 15 Symbol SBS Value Description Side band select. The image reject mixer can be programmed to either reject the image frequency at the LO upper frequency or at the LO lower frequency. It enables the user to have the RX LO in or out of ISM band and to use the same IC in both handset and base. 0* 1 14 to 13 EARP_VOL[1:0] frequency LO - IF is rejected frequency LO + IF is rejected Earpiece volume control. Software gain control on the earpiece amplifier is done with integrated switch feedback resistances. 00 01 10 11* 12 EARP 0* 1 11 to 7 6 RX_GAIN[4:0] SFS Rfbck = 14 k, Gctrl = 0 dB Rfbck = 24 k, Gctrl = 4.7 dB Rfbck = 41 k, Gctrl = 9.3 dB Rfbck = 70.2 k, Gctrl = 14 dB Earpiece earpiece disable earpiece enable; can be used in RX mode for specific feature RX gain setting 0 1111* for values, see Table 9 Second filter select. Depending on the features of the IF filters used, the user might not need to use the second IF filter. IF filters having 4.5 dB insertion loss are recommended. 0 1* 5 D_PHASE second IF filter not selected second IF filter selected Data phase shifter. The SBS bit is used to invert the phase of the data. Depending on the SBS bit value and the protocol chosen, the data can be inverted between the base and handset data transmission. To correct the data polarity, bit D_PHASE is set. 0* 1 4 to 0 FM_PLL_VCO[4:0] inverter is bypassed inverter is used PLL center frequency calibration. This programming allows calibration of the center frequency of the VCO within the FM PLL to align the frequency as close as possible to the nominal 10.7 MHz frequency. 0 1111* For values, see Table 10 SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 16 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC TX and RX gain RX_GAIN[4:0] and TX_GAIN[4:0] Bit 4 Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RX and TX gain (dB) -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 +0.5 +1.0 +1.5 +2.0 +2.5 +3.0 +3.5 +4.0 +4.5 +5.0 +5.5 +6.0 +6.5 +7.0 +7.5 +8.0 Earpiece output (dB) -15.0 -14.0 -13.0 -12.0 -11.0 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0 +1.0 +2.0 +3.0 +4.0 +5.0 +6.0 +7.0 +8.0 +9.0 +10.0 +11.0 +12.0 +13.0 +14.0 +15.0 +16.0 Table 9. Select 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 The TX and RX audio signal paths each have a programmable gain block. If a TX or RX voltage gain other than the nominal power-up default is desired, it can be programmed via the microcontroller interface. The gain blocks can be used during final test of the radio to electronically adjust for gain tolerances in the radio system. The RX and TX gain have steps of 0.5 dB covering a dynamic range from -7.5 dB to +8 dB. At the earpiece output, the RX gain steps are multiplied by 2 due to the expander slope. The volume control feature for the earpiece amplifier allows for compensation of gain tolerances from -15 dB to +16 dB. Volume control is preferably done on the earpiece amplifier (bits EARP_VOL[1:0]). SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 17 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC PLL center frequency calibration FM_PLL_VCO[4:0] Bit 4 Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +3.0 +2.8 +2.6 +2.4 +2.2 +2.0 +1.8 +1.6 +1.4 +1.2 +1.0 +0.8 +0.6 +0.4 +0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 -3.2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Center frequency shift (MHz) Table 10. Select 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 This programming allows calibration of the center frequency of the VCO within the FM PLL to align the frequency as close as possible to the nominal 10.7 MHz frequency. SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 18 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 8.2 Data register 1 Table 11. Data register 1 (address 001h) bit description Legend: * reset value. Bit 9 to 0 Symbol RX_MDIV[9:0] Value Description RX prescaler RX main divider 15 to 10 RX_PRE[5:0] 8.3 Data register 2 Table 12. Data register 2 (address 010h) bit description Legend: * reset value. Bit Symbol Value Description 00 undefined; must always be set logic 0 0000* Reference divider 15 to 10 reserved 9 to 0 REF_DIV[9:0] 8.4 Data register 3 Table 13. Data register 3 (address 011h) bit description Legend: * reset value. Bit 9 to 0 Symbol TX_MDIV[9:0] Value Description TX prescaler TX main divider 15 to 10 TX_PRE[5:0] 8.5 Data register 4 Table 14. Data register 4 (address 100h) bit description Legend: * reset value. Bit 15 Symbol TM2 Value Description 0* Test mode selection. Test mode bits are only used for test in production and application tuning. Those bits have to be set to logic 0 for normal operation. See Table 22. Clock output drive. Depending on the microcontroller clock frequency and clock capacitive load, the output CLKO can be programmed to optimize current consumption. The clock output level is 1.5 V (p-p). Output CLKO is AC-coupled with pin XTALI of the microcontroller. The external resonator from the microcontroller is then removed. 10 MHz at 10 pF 10 MHz at 5 pF (or 5 MHz at 10 pF) Test mode selection. Test mode bits are only used for test in production and application tuning. Those bits have to be set to logic 0 for normal operation. See Table 22. 14 CLKO 0* 0* 1 13 TM1 0* SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 19 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 14. Data register 4 (address 100h) bit description ...continued Legend: * reset value. Bit 12 Symbol DOUBLER Value Description Voltage doubler. The minimum supply voltage for the IC is 2.9 V which limits the voltage swing on both charge pumps to approximately 2.3 V. Using the voltage doubler or an external high supply voltage on pin VCP, allows the increased voltage range to enhance the tuning range of the VCO varicaps. To save current in Inactive mode, the voltage doubler clock frequency is the same as the CLKO clock (can be programmed to XTAL / 128); in Active mode, the voltage doubler clock is XTALI / 2. 0* 1 11 to 7 TX_GAIN[4:0] doubler inactive doubler active TX gain setting 01 for values, see Table 9 1111* 6 TX_MU 0 1* 5 HD_LIM 0* 1 5 ALC 0* 1 3 XTAL 0 1* 2 RX_MU 0 1* 1 DEM_FIL TX channel mute not muted (normal operation) muted Hard limiter disable enable Automatic level control enable (normal operation) disable Crystal oscillator on off RX channel mute not muted (normal operation) muted Demodulator filter. An internal programmable filter limits the demodulator bandwidth. The -3 dB cut-off frequency is selected with this bit. The wider bandwidth provides a solution for audio and sub-audio digital applications. 0* 1 0 reserved 0* 7 kHz 100 kHz undefined, must always be set to logic 0 SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 20 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 8.6 Data register 5 Table 15. Data register 5 (address 101h) bit description Legend: * reset value. Bit 15 Symbol REG 0 1* 14 MODE[1:0] 00* 01 10 11 13 XTAL_H Value Description Internal voltage regulator disable and tied to supply voltage VCC (in Inactive mode) enable Active mode selection. See details in Table 4 "Activated blocks". Inactive mode Inactive mode RX mode Active mode Crystal high current. In Inactive mode, the crystal oscillator is a major contributor to the full current consumption. 0 save current operation yields a full current consumption in Inactive mode at 230 A; see details in Section 7.1.3 "Control bits in power saving modes" crystal oscillator current is increased by 100 A Carrier detection threshold programming. When bit BAT_DET = 0, the carrier detector is enabled and the signal Carrier detection is routed to the output pin CDLBD. If RSSI is above the programmed RSSI level, pin CDLBD = LOW; if not then pin CDLBD = HIGH. The carrier detector gives an indication if a carrier signal is present on the selected channel. The nominal value and tolerance of the carrier detection threshold is given in the carrier detector specification. If a different carrier detection threshold value is desired, it can be programmed through the microcontroller interface. To scale the carrier detection range, connect an external resistor from pin RSSI to ground. The value 1 0011 corresponds to RSSI = 0.86 V (typical DC value). 0 For values, see Table 16 0000* 6 to 4 L_BAT_DET[2:0] Low battery detector voltage. When bit BAT_DET = 1, the low battery detector is enabled and the signal BDout is routed to the output pin CDLBD. If the supply voltage is below the programmed level, pin CDLBD = LOW and if not, pin CDLBD = VCC. 000* 001 010 011 100 101 110* 111 SA58646_1 1* 11 to 7 CAR_DET_LEV[4:0] 3.5 V 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2.8 V (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 21 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 15. Data register 5 (address 101h) bit description ...continued Legend: * reset value. Bit 3 Symbol BAT_DET 0 1* 2 to 0 CLK_DIV[2:0] Value Description Battery detection disable enable Clock output divider. The Clockout signal is derived from the crystal oscillator and is used to drive a microcontroller (bit CLKO). The crystal signal is divided down with a programmable divider value. To supply the clock to the microcontroller and save current in the handset, an external low power resonator may be used and with the clock output disable (bits CLK_DIV[2:0] = 000) as well as the crystal oscillator not active (bit XTAL = 1). In Power-saving mode, the divider ratio is programmed down to 128 to reduce the microcontroller power consumption. 100* Table 16. Select 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SA58646_1 for values, see Table 17 Carrier detection CAR_DET_LEV[4:0] Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.1 0.14 0.18 0.22 0.26 0.3 0.34 0.38 0.42 0.46 0.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82 0.86 0.9 0.94 0.98 1.02 (c) NXP B.V. 2007. All rights reserved. RSSI threshold detection voltage (V) Product data sheet Rev. 01 -- 8 February 2007 22 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Carrier detection ...continued CAR_DET_LEV[4:0] Bit 4 Bit 3 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 1.06 1.1 1.14 1.18 1.22 1.26 1.3 1.34 1 1 1 1 1 1 1 1 RSSI threshold detection voltage (V) Table 16. Select 24 25 26 27 28 29 30 31 Table 17. Select 1 2 3 4 5 6 Clock output divider CLK_DIV[2:0] Bit 2 0 0 0 0 1 1 Bit 1 0 0 1 1 0 1 Bit 0 0 1 0 1 0 1 output disable 2 2.5 4 1 128 Clock divider ratio 8.7 Data register 6 Table 18. Data register 6 (address 110h) bit description Legend: * reset value. Bit Symbol Value Description Power amplifier output level. The power amplifier uses 2 bits to modify the output power. The PA is disabled for value 000. Duplexer matching from 300 to 50 is implemented with a parallel inductor and series C network. To get the power at the antenna, the duplexer insertion loss should be subtracted. At maximum power, the DC current consumption is increased by 3 mA over the minimum power current consumption. 010* 12 TX_CP 0* 1 11 RX_CP 0* 1 The output power for a 50 termination is specified in Table 20. TX charge pump current. The performance of the PLL can be improved by increasing charge pump current. 400 A 800 A RX charge pump current. The performance of the PLL can be improved by increasing charge pump current. 400 A 800 A 15 to 13 PA_OUT[2:0] SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 23 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 18. Data register 6 (address 110h) bit description ...continued Legend: * reset value. Bit 10 to 8 Symbol REG_ADJ[2:0] Value Description Voltage regulator adjustment. An internal 1.5 V band gap voltage reference provides the voltage reference for the low battery detector circuits, the VREG regulator voltage, the VB reference voltage and all internal analog references. In Inactive mode, the adjustment is disabled. 011* 7 to 6 EXP[1:0] for values, see Table 21 Expander noise level control. Depending on the application noise floor specification, a noise level control can be applied. 00* 11 5 TM0 0* expander disabled expander maximum value Test mode selection. Test mode bits are only used for test in production and application tuning. Those bits have to be set to logic 0 for normal operation. See Table 22. undefined; must always be set to logic 0 Crystal tuning capacitors. An on-chip crystal reference tuning is provided to compensate for frequency spread over process and temperature. The value of the external capacitor on pin XTALI is chosen to be around 3 pF lower than on pin XTALO. Internally, a programmable capacitance is in parallel with pin XTALI. Tuning capacitance values are in the range of 0 pF to 4.5 pF. 0111* for values, see Table 19 Table 19. Select 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Crystal tuning capacitance XTAL_TUN[3:0] Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.2 0.5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 Capacitance (pF) 4 3 to 0 reserved XTAL_TUN[3:0] 0* SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 24 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Power amplifier output PA_OUT[2:0] Bit 2 Bit 1 Bit 0 Power amplifier Output power (dBm) PA inactive 1.0 1.9 2.5 3.0 Second harmonic (dBm) -17 -19 -23 -26 Third harmonic (dBm) -27 -29 -33 -36 Fourth harmonic (dBm) -34 -34 -36 -40 Table 20. Select 0 1 2 3 Table 21. Select 0 1 2 3 4 5 6 7 Table 22. TM2 0 0 0 0 1 1 1 1 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 Voltage reference adjust REG_ADJ[2:0] Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Test mode TM1 0 0 1 1 0 0 1 1 TM0 0 1 0 1 0 1 0 1 Select normal operation up or down RX up or down TX up or down RX or TX reference divider output divided by 2 prescaler and main divider RX divided by 2 prescaler and main divider TX divided by 2 double synthesizers charge pump are in 3-state Bit 0 0 1 0 1 0 1 0 1 -7 % -5 % -3 % -1 % +1 % +3 % +5 % +7 % Nominal voltage reference Out-of-lock of synthesizers RX or TX can be indirectly monitored on pin CDLBD: the width of the `glitch' gives a direct measure of the phase error on the PLL RX and/or PLL TX. To tune the external RX and TX VCO inductors, a defined divider ratio has to be programmed on the dividers, and then the image of the VCO frequency can be read on pin CDLBD. It can also be used to check the divider ratio: force a frequency on VCO or crystal pins and read the programmed frequency on pin CDLBD. Before pin CDLBD, there is a divide-by-2, then all frequencies are divided by 2. When charge pumps are in 3-state, the VCOs can be measured in stand-alone. SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 25 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 9. Limiting values Table 23. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Tstg Parameter supply voltage storage temperature Conditions Min -0.3 -55 Max +6.0 +125 Unit V C 10. Thermal characteristics Table 24. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 68 Unit K/W 11. Characteristics Table 25. Supplies VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol VCC Tamb Parameter supply voltage ambient temperature Conditions Min 2.9 -40 Typ 3.3 +25 Max 5.5 +85 Unit V C Table 26. Receiver part VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Low noise amplifier and image reject mixer (fo = 903 MHz) Input: pins RFIX and RFIY Ri(RF) RF input resistance real part of the parallel input impedance; balanced; indicative value imaginary part of the parallel input impedance; balanced; indicative value 110 Ci(RF) RF input capacitance - 0.7 - pF fi(RF) LNA |s11(RF)|2 Gp(conv) ICP1dB IP3 NF f(image) RF input frequency RF input return loss conversion power gain 1 dB input compression point third-order intercept point noise figure image frequency rejection overall RF front-end (does not include the IF section) in band of interest from balun input to pin MIXO matched to 330 [1] [1] 902 10 26 903 22 -23 -13 4 45 928 5 - MHz dB dB dBm dBm dB dB SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 26 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 26. Receiver part ...continued VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol RL CL Parameter load resistance load capacitance Conditions indicative value of IF resistive output load indicative value of IF capacitive output load SFS = 0 SFS = 1; measured at amplifier output first IF amplifier second IF amplifier NF noise figure IF amplifier first IF amplifier second IF amplifier PLL demodulator (fo = 10.7 MHz; f = 25 kHz; fmod = 1 kHz) B-3dB(demod) demodulator -3 dB bandwidth DEM_FIL = 0; loop filter: 4.7 k, 1.8 nF and 150 pF DEM_FIL =1; loop filter: 15 k, 150 pF and 12 pF VCO fVCO VCO frequency VCO center frequency (free running); open loop; all conditions after calibration 7.0 10.7 15.0 MHz 7 100 kHz kHz [2] [2] [2] [2] Min - Typ 330 - Max 3 Unit pF Output: pin MIXO IF amplifier section (fo = 10.7 MHz) G gain 43 dB - 22.5 25 7.5 7 14 - dB dB dB dB dB f frequency deviation - 760 200 32 75 - kHz kHz/V kHz fVCO/VVCO VCO frequency change to VCO voltage change ratio fVCO(step) Nstep(f_VCO) VCO frequency step number of VCO frequency steps load resistance RMS output voltage output voltage Output: pin DETO RL Vo(RMS) VO 5 TX mode; RL = 10 k; amplifier gain G = 10 adjust with microcontroller [3] 100 1.4 350 1.6 k mV V 1.2 SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 27 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 26. Receiver part ...continued VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit FM receiver system characteristics Conditions: fo = 903 MHz; f = 25 kHz; fmod = 1 kHz; DEM_F = 0; pin EARO: RL= 150 in series with 10 F (all with ITU-T filter) SRX receiver sensitivity measured at antenna with 3 dB duplexer insertion loss; B = 100 kHz RX mode; input level for 9 dB SINAD TX mode; PA = 10; VEARO = 200 mV (RMS); minimum TX-to-RX duplexer isolation = 35 dB S/N signal-to-noise ratio Vi(RF) = -80 dBm and -40 dBm; TX mode; PA_OUT[2:0] = 10; CLKO off; VEARO = 200 mV (RMS) at f = 60 kHz (without ITU-T filter); Vi(RF) = -80 dBm and -40 dBm; TX mode; PA_OUT[2:0] = 10; CLKO off; VEARO = 500 mV (RMS) on pin RSSI programmable through microcontroller -115 -113.5 dBm dBm 25 38 - dB THD total harmonic distortion - 0.6 2 % RSSI or carrier detection: VVB = 1.5 V Io(dyn) Nstep(th)(cd) Vdet Vhys Vdet(step) Rint dynamic output current number of carrier detect threshold steps detection voltage hysteresis voltage detection voltage step internal resistance measured between pin RSSI and VCC Vi(limiter) = 0 mV (RMS); RSSI threshold level = 0.86 V Vi(limiter) = 100 mV (RMS); RSSI threshold level = 0.86 V 0.05 68 32 45 40 175 1.6 V mV mV k dB Output: pin RSSI Output: pin CDLBD VOH VOL HIGH-level output voltage LOW-level output voltage 0.9VCC 0.1VCC V V Data comparator Input: pin DATAI Vi(p-p) Vhys(i) Vth Zi VOH SA58646_1 peak-to-peak input voltage input hysteresis voltage threshold voltage input impedance HIGH-level output voltage VDATAI = VCC - 1.4 V 100 25 150 0.9VCC 40 VCC - 0.9 240 - 75 - mV mV V k V Output: pin DATAO (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 28 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 26. Receiver part ...continued VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol VOL IO(sink) Parameter LOW-level output voltage output sink current Conditions VDATAI = VCC - 0.4 V VDATAI = VCC - 0.4 V; VDATAO = 0.1VCC free running Lext = 4.7 nH at 890 MHz; Lext = 3.9 nH at 935 MHz; control voltage VRXLF = 0.5 V VRXLF = 1.5 V n phase noise indicative value (cannot be directly measured foffset = 1 kHz foffset = 10 kHz foffset = 100 kHz Qmin minimum quality factor external inductor quality factor at 920 MHz; Lext = 3.9 nH [4] [1] Min - Typ 50 Max 0.1VCC - Unit V A RX voltage controlled oscillator fVCO VCO frequency 910 MHz fVCO/VVCO VCO frequency change to VCO voltage change ratio - 50 30 - MHz/V MHz/V 30 -58 -82 -102 - - dBc/Hz dBc/Hz dBc/Hz [1] [2] [3] [4] This specification will be measured and guaranteed only on the NXP Semiconductors SA58646 board. 330 matched input and output. The level on pin RXAI will be higher in RX mode than in TX mode. Conditions: carrier = 892.3 MHz; Lext = 4.7 nH (3.9 nH for 935 MHz operation); loop filter: C1 = 3.9 nF; R2 = 6.8 k; C2 = 47 nF (see application note). Table 27. Transmitter part VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Summator amplifier Input: pin MODI Vbias Vo(p-p) Rfbck fVCO bias voltage peak-to-peak output voltage feedback resistance VCO frequency between pins MODI and MODO free running control voltage VTXLF = 0.5 V VTXLF = 1.5 V modulation voltage VMODO = 2.2 V 530 kHz/V 50 25 MHz/V MHz/V [1] 10 - 2.2 94 910 240 - V mV k MHz Output: pin MODO TX voltage controlled oscillator fVCO/VVCO VCO frequency change to VCO voltage change ratio SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 29 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 27. Transmitter part ...continued VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol n Parameter phase noise Conditions VCO TX plus PA; output power at 0 dB foffset = 20 MHz foffset = 10 kHz foffset = 1 kHz Qmin minimum quality factor external inductor quality factor at 902 MHz to 928 MHz; Lext = 3.9 nH subtract duplexer insertion loss to get power on antenna; see Table 20 see Table 20 software control [3] [2] Min Typ Max Unit -139 30 -150 -85 -60 - - dBc/Hz dBc/Hz dBc/Hz Power amplifier Po Po Nstep(G_adj) output power output power variation number of gain adjustment steps total harmonic distortion 3 2 4 dBm dB [3] Transmit system THD measured after demodulation; VMODO for demodulated f = 60 kHz; measured with ITU-T filter RX VCO spurious emission on PA output versus output power [1] - 1 2 % Psp spurious output power - -45 - dBc [1] [2] [3] This specification will be measured and guaranteed only on the NXP Semiconductors SA58646 board. TX-to-RX duplexer isolation = 35 dB; carrier = 925.6 MHz; Lext = 3.9 nH (for both base and handset); loop filter: C1 = 470 nF, R2 = 1.8 k and C2 = 4.7 F (see application note). Load: R = 50 ; Lp = 22 nH; Cs = 1.6 pF. Table 28. Synthesizer VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol fxtal Ci(XTALI) Ci(XTALO) Ctune(xtal) Nstep(C_tune) Clock divider D/Dclk tsw clock divider ratio switching time CLK_DIV[2:0] from one frequency f1 to frequency f2 external load 1 2 / f2 128 s Parameter crystal frequency input capacitance on pin XTALI input capacitance on pin XTALO crystal tuning capacitance Conditions reference input frequency indicative; XTAL_TUN[3:0] = 8 indicative on pin XTALI Min 4 Typ 10.24 4 1.5 4.5 16 Max 20 Unit MHz pF pF pF Crystal oscillator; external capacitors on pins XTALO = 8.2 pF and XTALI = 5.6 pF (indicative) number of tuning capacitance XTAL_TUN[3:0] steps Output: pin CLKO CL load capacitance 20 pF SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 30 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 28. Synthesizer ...continued VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol Vo(p-p) Parameter peak-to-peak output voltage Conditions CLKO = 1; 10 MHz at 5 pF (or 5 MHz at 10 pF) CLKO = 0; 10 MHz at 10 pF 10-bit reference divider D/Dref fi(RF) D/Dmain D/Dps Io(cp) Co VO(VCP) reference divider ratio RF input frequency main divider ratio prescaler divider ratio charge pump output current output capacitance output voltage on pin VCP DOUBLER = 1; VCC = 3 V RX_MDIV[9:0]; TX_MDIV[9:0] RX_PRE[5:0]; TX_PRE[5:0] RX_CP = 0; TX_CP = 0 RX_CP = 1; TX_CP = 1 Voltage doubler 5.2 V REF_DIV[9:0] 8 902 8 64 903 400 800 1023 928 1023 127 8 A A pF MHz TX and RX prescaler and main dividers Min Typ 1.5 1.5 Max Unit V V RX and TX charge pump: pins RXPD and TXPD Table 29. RX baseband VCC = 3.3 V; Tamb = 25 C; see Figure 6. VVB = 1.5 V; fi = 1 kHz; RX gain set for 0 dB gain at -20 dBV on pin RXAI; earpiece volume at +4.7 dB; 560 pF between pins EARI and EARO; 150 in series with 10 F on pin EARO; all measured with a ITU-T filter except THD; unless otherwise specified. Symbol THD NFM Vi(max) Zi Parameter total harmonic distortion peak noise figure maximum input voltage input impedance Conditions VRXAI = -20 dBV B = 300 Hz to 3.4 kHz THD < 4 % in TX mode in RX mode RX audio gain adjust Gadj gain adjustment range RX_GAIN[4:0] on RX gain amplifier on pin EARO Nstep(G_adj) mute Expander Gexpdr expander gain VRXAI = -20 dBV -1 0 +1 dB number of gain adjustment steps mute attenuation VRXAI = -20 dBV -7.5 -15 32 -70 +8 +16 -60 dB dB dB [1] [1] Min 100 Typ 0.2 -83 13 15 - Max 2 - Unit % dBV dBV k k RX audio path: RX gain adjust, mute and expander Input: pin RXAI SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 31 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 29. RX baseband ...continued VCC = 3.3 V; Tamb = 25 C; see Figure 6. VVB = 1.5 V; fi = 1 kHz; RX gain set for 0 dB gain at -20 dBV on pin RXAI; earpiece volume at +4.7 dB; 560 pF between pins EARI and EARO; 150 in series with 10 F on pin EARO; all measured with a ITU-T filter except THD; unless otherwise specified. Symbol Gexpdr Parameter expander gain change Conditions referenced to VRXAI = -20 dBV with RX baseband audio noise tuning VRXAI = -30 dBV VRXAI = -35 dBV VRXAI = -45 dBV tatt(expdr) trel(expdr) expander attack time expander release time CECAP = 0.47 F CECAP = 0.47 F from pins CMPI to EARO; VCMPI = -20 dBV; VRXAI = 0 V (RMS) indicative value; THD < 4 % [2] Min Typ Max Unit -24 -37 - -20 -30 -47 2.0 5.0 80 -18 -26 -45 - dB dB dB ms ms dB ct(compr-expdr) compressor to expander crosstalk attenuation Vo(max) Gctrl(dyn) Gctrl maximum output voltage dynamic gain control gain control 13 -7 14 15 dBV dB Earpiece amplifier no external resistor or capacitor used EARP_VOL[1:0] = 00 EARP_VOL[1:0] = 01 EARP_VOL[1:0] = 10 EARP_VOL[1:0] = 11 Output: pin EARO Vo(p-p) RL peak-to-peak output voltage load resistance THD < 4 % to keep amplifier stability; RL in series with 10 F 2.2 150 100000 V -1 3.7 8.3 13 0 4.7 9.3 14 +1 5.7 10.3 15 dB dB dB dB [1] [2] Pin RXAI level will be higher in RX mode than in TX mode. With expander output noise level control tuned for -65 dBV (max) and maximum gain tolerance of -4 dB at -35 dBV. With a larger gain tolerance at -35 dBV, the typical output noise can be reduced by 10 dB. See application note. Table 30. TX baseband VCC = 3.3 V; Tamb = 25 C; see Figure 8. VVB = 1.5 V; fi = 1 kHz; TX gain set for +10 dB gain at -30 dBV on pin CMPI; unless otherwise specified. Symbol G Vo(max) Zi Compressor G gain VCMPI = -30 dBV; ALC off; hard limiter enabled 9 10 11 dB Parameter gain maximum output voltage input impedance RL = 10 k; THD < 0.2 % Conditions Min 0 -12 Typ 15 Max 34 Unit dB dBV k Microphone amplifier Output: pin MICO Input: pin CMPI SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 32 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 30. TX baseband ...continued VCC = 3.3 V; Tamb = 25 C; see Figure 8. VVB = 1.5 V; fi = 1 kHz; TX gain set for +10 dB gain at -30 dBV on pin CMPI; unless otherwise specified. Symbol G Parameter gain deviation Conditions referenced to VCMPI = -30 dBV VCMPI = -10 dBV VCMPI = -50 dBV Gmax THD tatt(compr) trel(compr) Hard limiter Vo(p-p) TX mute mute Gadj Nstep(G_adj) mute attenuation gain adjustment range number of gain adjustment steps from pins RXAI to TXO; VRXAI = -10 dBV; VCMPI = 0 V (RMS) ALC on VCMPI = -12 dBV VCMPI = -10 dBV VCMPI = -2.5 dBV Table 31. Other features VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol VO Parameter output voltage Conditions voltage regulator disabled voltage regulator enabled before Vref adjustment or in Inactive mode after Vref adjustment IO Vdet Vhys Nstep(V_det) output current detection voltage hysteresis voltage number of detection voltage steps CVREG = 1 F L_BAT_DET[2:0] [1] Min 8 -14 - Typ 10 -10 23 0.5 4.0 8.0 1.26 Max 12 -8 2 - Unit dB dB dB % ms ms V maximum gain total harmonic distortion compressor attack time compressor release time peak-to-peak output voltage VCMPI = -70 dBV VCMPI = -10 dBV; ALC off CCCAP = 0.47 F CCCAP = 0.47 F VCMPI = -4 dBV; ALC off; hard limiter enabled VCMPI = -10 dBV; ALC off RX_GAIN[4:0] -7.5 - -70 32 -60 +8 - dB dB TX gain adjust Output: pin TXO ct(expdr-compr) expander to compressor crosstalk attenuation Zo Vo(max) output impedance maximum output voltage 65 dB - 500 -12.5 -12.3 -11.5 - dBV dBV dBV Min 2.5 2.65 2.8 - Typ VCC 2.7 2.7 18 8 Max 2.9 2.75 3 3.5 - Unit V V V mA V mV PLL voltage regulator: pin VREG Low battery detector: battery detection enabled SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 33 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC Table 31. Other features ...continued VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol VCC/VCC Parameter supply voltage variation to supply voltage ratio Conditions battery voltage detection accuracy after Vref adjust; L_BAT_DET[2:0] = 010 (VCC = 3 V) Min Typ 0.5 Max 5 Unit % Output: pin CDLBD IOL VOL VOH LOW-level output current LOW-level output voltage HIGH-level output voltage RL = 470 k RL = 470 k 20 0.9VCC 0.1VCC mA V V [1] V VB V hys = ( V high - V low ) x --------V th Table 32. Microcontroller serial interface VCC = 3.3 V; Tamb = 25 C; unless otherwise specified. Symbol VIL VIH IIL IIH Ci tsu(CLK-EN) tsu(DATA-CLK) th(EN-CLK) fclk tr(i) tf(i) th(CLK-EN) tw(EN) tstartup(MCU) Parameter LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance CLK to EN set-up time DATA to CLK set-up time EN to CLK hold time clock frequency input rise time input fall time CLK to EN hold time pulse width on pin EN MCU start-up time 90 % of VVREG to pins DATA, CLK and EN at 10 % to 90 % on pins DATA, CLK and EN; at 10 % to 90 % on pins DATA, CLK and EN; at end of word [1] Conditions Min VVREG / 1.5 Typ - Max 0.5 VCC 5 8 3 50 50 200 Unit V V mA mA pF ns ns ns MHz ns ns ns ns s Input and output: pins DATA, CLK and EN VIL = 0.3 V VIH = VVREG - 0.3 V -5 - Timing (see Figure 10) 50 % of signals 50 % of signals 50 % of signals 50 50 50 100 1 / fcomp - [1] The minimum pulse width tw(EN) should be equal to the period time of the comparison frequency. The synthesizer ensures that the internal EN signal does not occur during a comparison phase to avoid any phase error jump. This time can be reduced to 100 ns for: a) Clock divider programming b) Synthesizer programming: only for words which do not influence the synthesizer (word 1, 2, 3) SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 34 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC data bits (16) DATA D15 tsu(DATA-CLK) CLK D13 D12 AD1 address bits (3) AD0 50 % tsu(CLK-EN) 50 % tw(EN) th(EN-CLK) th(CLK-EN) EN 50 % data bits latched 001aaf625 Fig 10. Digital signal timing C 1.0 0.8 0.6 0.4 0.2 0 0 0.5 1.0 2.0 3.0 4.0 5.0 V 001aaf627 Fig 11. Varicap behavior SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 35 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 12. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 12. Package outline SOT314-2 (LQFP64)) SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 36 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 13. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 14.3 Wave soldering Key characteristics in wave soldering are: SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 37 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 33 and 34 Table 33. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 34. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 38 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 15. Abbreviations Table 35. Acronym ALC BiCMOS CMOS ESD FM IF ISM LNA LO LPF PA PCB PLL RF RSSI SINAD VCO Abbreviations Description Automatic Level Control Bipolar Complementary Metal Oxide Semiconductor Complementary Metal Oxide Semiconductor ElectroStatic Discharge Frequency Modulation Intermediate Frequency Industrial, Medical and Scientific Low Noise Amplifier Local Oscillator Low-Pass Filter Power Amplifier Printed-Circuit Board Phase-Locked Loop Radio Frequency Received Signal Strength Indicator Signal-plus-Noise-And-Distortion to noise-plus-distortion ratio Voltage Controlled Oscillator SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 39 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 16. Revision history Table 36. Revision history Release date 20070208 Data sheet status Product data sheet Change notice Supersedes Document ID SA58646_1 SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 40 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com SA58646_1 (c) NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 -- 8 February 2007 41 of 42 NXP Semiconductors SA58646 UHF 900 MHz transceiver IC 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.7.2 7.8 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 7 Power supply and power management. . . . . . . 7 Power supply voltage . . . . . . . . . . . . . . . . . . . . 7 Power-saving operation modes. . . . . . . . . . . . . 7 Control bits in power saving modes . . . . . . . . . 8 FM receiver part . . . . . . . . . . . . . . . . . . . . . . . . 9 Transmitter part. . . . . . . . . . . . . . . . . . . . . . . . 10 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 RX baseband . . . . . . . . . . . . . . . . . . . . . . . . . 12 TX baseband . . . . . . . . . . . . . . . . . . . . . . . . . 13 Other features. . . . . . . . . . . . . . . . . . . . . . . . . 14 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 14 Low battery detector . . . . . . . . . . . . . . . . . . . . 14 Microcontroller serial interface . . . . . . . . . . . . 14 Data registers and addresses. . . . . . . . . . . . . 14 Data register 0 . . . . . . . . . . . . . . . . . . . . . . . . 16 Data register 1 . . . . . . . . . . . . . . . . . . . . . . . . 19 Data register 2 . . . . . . . . . . . . . . . . . . . . . . . . 19 Data register 3 . . . . . . . . . . . . . . . . . . . . . . . . 19 Data register 4 . . . . . . . . . . . . . . . . . . . . . . . . 19 Data register 5 . . . . . . . . . . . . . . . . . . . . . . . . 21 Data register 6 . . . . . . . . . . . . . . . . . . . . . . . . 23 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal characteristics. . . . . . . . . . . . . . . . . . 26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 36 Handling information. . . . . . . . . . . . . . . . . . . . 37 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Introduction to soldering . . . . . . . . . . . . . . . . . 37 Wave and reflow soldering . . . . . . . . . . . . . . . 37 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 37 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 38 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 40 Legal information. . . . . . . . . . . . . . . . . . . . . . . 41 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17.3 17.4 18 19 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 41 42 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 February 2007 Document identifier: SA58646_1 |
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